iBex_fdiv single precision floation point divider ASIC/FPGA core

Important Features

·     Single cycle floating point divider, IEEE 754 compliant 

·     Over 30MHz on Xilinx FPGA, Intel FPGA and 180nm ASIC

·     Single clock synchronous design

·     Can be reconfigured for 300 MHz in pipeline (18 pipeline stages)

·     3.8K ASIC gates, 2413 Intel FPGA ALMs and  2595 Xilinx LUTs.

Deliverables

 ‧  Synthesizable verilog source code
 ‧  Verilog testbench

Interface